Binary counter



United States Patent O 3,264,455 BINARY COUNTER .Elmar Gdtz, Frankfurt-Gravenbruch, Germany, assignor to Licentia Patents-Verwaltungs-G.m.b.H., Frankfurt am Main, Germany Filed Jan. 9, 1963, Ser. No. 250,341 Cla'ims'priority, application Germany, Jan. 9, 1962,

3 Claims. a. 235-9 2 stages step down the voltage in the ratio 1:2, so that a correspondingly decreased square wave voltage appears at the output of the flip-flop stage. This voltage, in turn, is applied as the control voltage of a further flip-flop stage, at whoseoutput a further stepped down square wave voltage 'appea'rs. If such binary counters are fashioned as static flip-flop stages, certain difficulties will, under certain circumstances, arise in the transfer characteristics when the individual stages change their state. These stages might then assume the incorrect state. In the case of a binary counter incorporating dynamic capacitatively coupled flip-flop stages, the respective coupling capacitors between the several stages take over, i.e., store the time delay of the control signal, so that the transfer characteristics of the stages will not cause any difficulties. However, the drawback of capacitatively coupled stages is that the same respond not only to the actual control signals and clock pulses, but also to extraneously generated spurious pulses.

It is, therefore, an object of the present invention to overcome the above disadvantage, and, with this object in view, the present invention resides in an electronic binary counter at whose output natural binary code signals appear in parallel representation, i.e., simultaneously, which counter is characterized, basically, by the following features: (1) there are adders associated with each binary digit (2, 2 2 2 the carry circuits of which adders are coupled to each other galvanically, (2) the sum signals of the adders (L or 0, where L represents binary l) are applied to output storage devices which are capable of having clock pulses applied to them, which storage devices feed these sum signals back into the same adders. and (3) one of the binary signals applied to the adder of the lowest order binary digit constantly has the value L.

According to another feature of the present invention, the adders are half-adders.

According to still another feature, an intermediate storage device is provided which is capable of being operated by a clock pulse, which intermediate storage device is connected between the output storage device and the adder pertaining thereto.

According to yet another feature of the present invention, the adders are split up in such a manner that the transfer circuit is cut into the circuit arrangement ahead of the intermediate storage device which then additionally acts as an amplifier, and that the sum circuit is cut ahead of the output storage device which then also additionally acts as an amplifier. The carry and sum signals are formed and amplified by two similar logic circuits comprising AND circuits and OR/ OR NOT circuits.

According to still another feature of the present invention, the carry circuit comprises three AND circuits acting as a holding stage, a transient shunt stage, and an input stage, respectively, and the intermediate storage device comprises an OR/OR NOT circuit, which three AND 3,254,455 Patented August 2, 1966 circuits have their outputs connected to the OR/ OR NOT circuit from whose affirmed output the outgoing carry signalis derived. The sum circuit likewise comprises three AND circuits acting as a holding stage, a transient shunt stage, and an input stage, respectively, and the output storage device comprises a further OR/ OR NOT circuit, which three last-mentioned AND circuits have their outputs connected to the last-mentioned OR/OR NOT circuit at whose affirmed output there appears the result of the sum formation. The input and shunt stages of the carry circuit are connected to the output of the respective 'output storage device to receive the sum signal and also to receive the incoming carry signal arriving from the preceding digit, the input stage of the sum circuit is connected to receive the incoming carry signal arriving from the preceding digit and also to receive the negated outgoing carry signal, and the shunt stage of the sum circuit is connected to receive the negated outgoing carry signal and to the output of the respective output storage device to receive the sum signal.

Additional objects and advantages of the present invention will become apparent upon consideration of the following description when taken in conjunction with the accompanying drawings in which:

FIGURE 1 is a schematic diagram showing a basic unit pertaining to one binary digit.

FIGURE 2 shows the timed relationship of clock pulse trains used in the operation of the counter according to the present invention.

FIGURE 3 shows three digits of a counter incorporating three units associated with the respective digits.

FIGURE 4 is a schematic diagram showing a modified embodiment of a basic unit forming part of a counter according to the present invention.

FIGURE 5 shows two interconnected units according to FIGURE 4.

FIGURE 6 shows the details of an adder used in the counter according to the present invention.

FIGURE 7 shows the details of a half-adder used in the counter according to the present invention.

FIGURE 8 shows the details of one embodiment of a unit incorporated in a counter according to the present invention.

FIGURE 9 shows a sub-assembly incorporated in the unit of FIGURE 8.

FIGURE 10 shows the timed relationship of the pulse trains and the erasing pulse used in the operation of the embodiment of FIGURES 8 and 9.

FIGURES 11, 12, 13, 14, and 15 are Tables 1, 2, 3, 4, and 4a, respectively, which will be referred to for explanatory purposes.

Referring now to the drawings, FIGURE 1 shows a binary counter according to the present invention which uses an adder whose output signal s, is applied into an output storage device AS. The adder comprises a sum circuit whose inputs a, b, w have binary signals (L or 0) applied to them, while the result of the sum formation appears at the output terminal s,. The adder further includes a carry circuit having an output terminal u,,. g

A binary number a and b is applied to the adder If there is a carry from the preceding digit, such carry is applied to input u of the adder. As indicated above, these inputs are voltage signals of given polarity which correspond to the values '0 or L. The result signal is taken from the output a, of the output storage device AS. According to the present invention, one of the input signals of the adder of the lowest binary digit always has the value L.

The output storage device AS, being a clock pulsable component, is opened, at a given instant, by means of a timing or clock pulse t As soon as this clock pulse 1 J (for example L) appears, the sum of the adder is -taken over by the. output storage, deviceAS. The result appearing at'the output a, is additionally fed back and applied to an intermediate storage device ZS, the latter also being clock pulsable and controlled by a further clock pulse t The clock pulses t t are staggered, as shown in FIGURE 2. Thus, when a certain result appears at the output: storage device AS and hence at output terminal a, (L .or such result is applied, viaa line a',,, to the intermediate storage device ZS. The samev result will, at. clock pulse 1 appear in this intermediate storage. device and hence at a. As stated above, the adder forms the sum -a +b. Let the value a, in this case,'be the value coming from theintermediate-storage device ZS, and .let the value b in this case (the adder being that of the lowestbinary digit) always be the value L. The adder. then forms a+b,.and since b is always equal to L, the value formed will always be aI-L. This value is then applied, at clock pulse t to the output storage device. AS via line s,, Furthermore, the adder will form a carry which appears at output u In the instant example, the valueof the incoming carry use-=0.

The circuit arrangement depicted in FIGURE 1 and incorresponding to the circuitry of FIGURE 1, itabeing obvious that any suitable number of such units canbe provided. In each case, each unit will include the adder an output storage device AS connected to the output of the adder, and an intermediate storage device ZS to which the output value is fed back. The storage devices AS and ZS of each of the three units are operated by the same clock pulses t t respectively. The outgoingcarry formed in any one adder is applied to the adder. of the b a and the sum output s, the output storage device AS whose input is connected withthe output s of the adder and- Which has a result output 11, and the intermediate storage device ZS whose input is connected with the output a via lead a',, The output of-the intermediate storage device-ZS is connected with the input 0 of the adder The adder also has an output a for the outgoing carry which is applied to the unit pertaining to the next digit.

The units pertaining to the subsequent digits are characterized by the same basic reference numerals, except that they incorporate, instead out the subscripts O, the subscripts I and 2, respectively. In each case, the result outputs 0,0, (1, a,;, are fed back to the adders via respective intermediate storage devices. In adder the value. applied to the carry input M is equal to 0, as indicated within the parentheses, while the input b has the value L applied to it and the inputs b and b each have the value 0 applied -to them. There will thus be formed inthe adder In the above equation, s, represents the sum of a +b while u represents the outgoing carry. FIGURE 11,

containing Table 1, shows therelationship for a full adder.

If the three input values=0, the sum .9 and the outgo? ing carry will also be equal to 0. If each of the inputs a and b has the value 0 and the input u has the value L, the sum will be L while the outgoing carry will be 0, If only input b has the value L, the sum s again will be L, while theoutgoing carry is 0. If both inputs b and u, have the value L, the sum s will have the value 0 while the outgoing carry u =Lq Ifall three inputs have the value L, then the sum s= L and the outgoing carry I/t =L.

The circuit of FIGURE 3 can be simplified if the input b too, has applied to itnot the value L but the i value 0 and, instead, the carry u fior the lowest binary digit is always. made equal to L, as indicated at there? spective inputs (thevalues shown not in parentheses)., In this case the adders to can betfashioned as half-' adders. a

The inputs b to" b will thus always have the values 0 applied tothem. In this case, the first incoming carry u =L, as shown. This produces the substantial advantage that all of the units pertainingto the individual digits can be simplified and be made completely alike to .each' Insofar as Table 1 (FIGURE '11) is concerned, this means that, thanks to the fact. that the .valuefor other.

the carry u is fixedand the value 0 is applied to the inputs b to b the value for b will always be 0,- i.e;, all of those combinations in which b has [the .value L will never appear. .The values for input b which thusdrop out are, in Table 1, encircled by dashed lines. Table 2 (FIGURE 12) shows the remaining combinations: It' will be seen .thatthe input b is completely eliminated,

and all that remains are the four showucombinations. The third, fourth, seventh and eighth combinations of Table 1 are eliminated because :here theinput=b has up,

ing been equal to Table 2 represents the function of a half-adder.

Table 3 (FIGURE. 13)" again shows the formation of the sum by means-of the adders, operating on the basis of. the combinations shown in Table 2.,

000L=decimal 1. t the value L of the carry a is added. This produces the sum 0L0=decimal 2. The carry u is thereafter again added so as to produce the sum 0LL=decimal 3, and so on. Depending on the sequence of clock pulses t there thus appears at the outputs a,, a of the counter of FIGURE 3 either the value 0 or ,the value L and the complete result of the counting operation can then be read, from the output of the lowest binary digit ((1, to the output of the highest binary digit (a or a as the case may be). The output (2, has the valuation 2 the output (1, the valuation 2 the output 11, the valuation 2 and so on.

Table 4 (FIGURE 14) gives a tabular representation of the operation of the circuit, while FIGURE 4a (FIG- URE 15) gives the decimal equivalent outputs derived from the output signals at outputs 61, to a,,

In the. counter of FIGURE 3, the starting position of all of the units pertaining to the respective digits are in the state .0. Upon occurrence of the: first clock pulse t the incoming carry n L is transferred into the output storagedevice A8 The succeedingunits are all in the same state as they were before, namely 0, because the outgoing carry u =0. Upon occurrence of the first clock pulse t the result appearing at the outbut a, is applied to the intermediate storage device ZS whereupon this result also appears at the input a of the adder The contents L of the intermediate storage device ZS land the incoming carry u =L produces, in this state of the counter, an output s, =0 with an out-v going carry zl =L. As is apparentafrom Table 4, this carry is due .to the fact that the input a and the input u will, after the occurrence of the first clock pulse t In Table 3, the starting position is indicated by 0000. In the lowera V most;(0 digit, there will appear, at clock pulse t the incoming ca'rryu =L. This produces the sum UPOIIEOCCUI'IGHCB of the clockpulse.

each have the value L. The output s, of the adder will then, due to the outgoing carry u =L of the first adder and the value 0 at the inputs a 17 of the second adder have the value L. There then follows the second clock pulse 1 upon the occurrence of which the sum s,, L will appear, as result L, at the output a,,, of the adder The value L which is constantly applied to the input u is added, under the influence of the clock pulse train of pulses t with the value appearing at the input a of the first adder and the sum is then put out, while the value 0 or L at the carry output is passed on to the carry input ofthe next adder Table 4a shows the binary signals appearing at the outputs a a,,,, 11, at clock pulses t through i As explained above, the counter of FIGURE 3 can be expanded. For example, a further pulsable output storage device can be connected to adder which lastmentioned storage device is subjected to a further train of clock pulses and commences to add at a later instant. The counter of FIGURE 3 shows that the value L is added to the star-ting value as often as there is a clock pulse signal t =L.

The half adders of FIGURE 3 carry out two operations, namely, the formation of the sum and the formation of the outgoing carry. Accordingly, each half-adder has two outputs s, u,,. The outgoing carry is always applied to the next adder, whose carry, in turn, is applied to. the next following adder. As a result, the carry signal becomes progressively weaker. In order to avoid this, the carry paths between the adders and have to be equipped with special amplifiers, indicated at V in FIGURE 3 in dashed lines. In this way, the outgoing carry signal may be brought to the necessary strength. However, the amplifiers increase the expense of the counter, and, While an arrangement incorporating such amplifiers would be operative, it is desirable, if possible, to make do without these amplifiers, and according to another feature of the present invention, these amplifiers can be dispensed with by splitting up the formation of the sum and carry signals. This feature of the present invention is based on the following considerations: the counted result of a particular binary digit is present in an output storage device pertaining to the particular digit. This result is fed back into the respective intermediate storage device. The sum and the outgoing carry are thereafter formed separately, in contradistinction to the operation of FIGURE 3. This separate sum and carry formation is shown in FIGURE 4, in which the carry a is formed ahead of the intermediate storage device ZS. The intermediate storage device ZS is also used for forming the sum. The sum is then applied to the output storage device AS. The result appearing at the output of storage device AS is then fed back to the carry stage u. Also, the carry u coming from the preceding stage is applied to the carry forming stage it and the sum forming stage s. The carry 11,, for the following uni-t is derived from the output of the intermediate storage device ZS.

In the adding process, both the sum as well as the carry have to be formed. Both processes make use of the output a, and the input carry u As shown in FIG- URE 4, the value a, goes, via the carry stage u and the intermediate storage device ZS, to the sum stage s. The outgoing carry and the sum are thus formed separately. The carry stage it has a, and u applied to it, exactly as in the case of the adder of FIGURE 3. The arrangement of FIGURE 4, however, makes it possible to dispense with the amplifiers V which, in practice, would be needed for the circuit arrangement according to FIGURE 3, the reason for this being that the intermediate storage device ZS of each binary digit can take over this amplifying function. The carry, in FIGURE 4, is formed by the carry stage it which itself does not have any amplifying means, it being the intermediate storage de- 6 vice ZS which amplifies the outgoing carry signal u,,,.

The same effect is achieved by the fact that the sum is formed in the sum stage s which itself likewise has no amplifying means, it being the output storage device AS which acts as an amplifier for amplifying the output signals, of the sum stage s.

FIGURE 5 shows a counter for two binary digits, which counter can, of course, be expanded to as many digits as desired. Each unit of the counter of FIGURE 4 corresponds to the unit shown in FIGURE 3, the first unit including two storage device ZS A5, A nonamplifying sum stage s for forming the sum is connected ahead of the output storage device AS there being a nonamplifying carry stage u for forming the outgoing carry connected ahead of the intermediate storage device ZS The outgoing carry u is applied to the succeeding carry stage u and sum stage s The carry stage u, has its output connected to the input of the intermediate storage device ZS while the output of sum stage s is connected to the input of the output storage device AS For purposes of sum formation, the output value a is fed back to the arry age l- It will be seen from the above that, in the counter of FIGURE 5, the adder of each unit of FIGURE 3 is, in effect, divided into independent sum and carry stages without amplification, the intermediate storage device now being additionally used as a means for amplifying the carry signal while the output storage device is additionally used as a means for amplifying the sum signal. The sum and outgoing carry results are thus available for further processing.

It will be understood that the carry stages u according to the embodiments of FIGURES 4 and 5 do not constitute elements above and beyond the adders of FIGURE 3. The carry stages u of FIGURES 4 and 5 are already part of the adders of FIGURE 3. The same applies to the sum stages s. For purposes of illustration, FIGURE 6 shows the adder of FIGURE 3 with its component sub-parts.

What is involved is a half-adder whose principle of operation was explained in conjunction with Table 2. As can be seen from that table, a carry u =L appears when a, and u ,,==L. FIGURE 7 shows, in schematic form, one embodiment of such a half-adder. An AND circuit &' is provided which serves for forming the carry, the inputs of this AND circuit having the values a, and li applied thereto. The output of this AND circuit & produces the outgoing carry u,,,. This AND circuit does not amplify the carry signal; if such amplification is to be obtained, two amplifier stages, for example transistorized NOT circuits, would have to be provided, as indicated by stages N and N.

According to Table 2, s=L when a, and u have opposite values. Two additional AND circuits &", &"" are provided in the adder according to FIGURE 7 for purposes of forming the sum. The value L appears at the output of AND circuit &" when the input values of this circuit are u ,,=L and E,=L. The output of AND circuit &-' will be L when the input values are a,,=L and fi ,=L. Thus, in both cases will the sum be L. The outputs of the AND circuits &", &"' are connected to an OR circuit v. The lines lea-ding to E, and H each incorporate a NO'[ circuit N", N', as shown in dashed lines. The arrangement consisting of the above-described components constitutes, for example, the adder of FIGURE 3. It wil' be seen that each adder requires four NOT circuits N, N N", N-". In the case of the counters according to FIG- URES 4 and 5, these NOT circuits are eliminated, anc' their functions are taken over by the intermediate and output storage devices which must in any case be provided.

FIGURES 8 and 9 show the details of the counter 01 FIGURES 4 and 5. More particularly, the circuit arrangement of FIGURE 8 corresponds to that of FIGURE 4 and illustrates a single unit of the counter pertaining tc me binary digit. The unit usesstorage devices whose hange-over characteristics (signal changes from Lto r vice versa) are such that they will not assume the wrong ircuit condition (L or 0). FIGURE, 9 shows a sub- .ssembly of the unit of FIGURE 8, which subassembly :omprises three AND circuits 8: & & whose outputs re applied to an OR circuit v, the output of the latter, in

urn, being connected to an OR NOT circuit E. The three IND circuits constitute either the carry circuit u or; the,

um circuit s of FIGURE 4, while the OR/ OR NOT ciruit v, E, constitutes the appropriate storage device, i.e.,

he intermediate storage. device ZS if the three AND cir-1 uits are the carry circuit u or the output storage device lulse 7. The AND circuit & has applied to it the afiirmed lock pulse 1 and the input value e to be stored (L or 0).-

Vhen the clock pulse =L (at which time and the nput signal e=L, the output value of AND circuit 8: will qual L. This value is applied by OR circuit v to the OR. JOT circuit E and appears, at output a, as the signal L.

.he signal at output a will then be equal to L, while the ignal at output 5 will be equal .to 0. When the storage levice is in this condition, the values applied to the two nputs of AND circuit & will be L, so that the output of his AND circuit & will likewise be L. It matters not if he clock pulse 1- then becomes 0 (whereupon becomes because the value at output a is safely maintained t L by the AND circuit & during the.time the clock ulses 7-, 7, change their respective values. The AND ircuit & thus serves as a temporary or transient shunt. n general, the signal e lasts longer than the clock pulse 1, .nd thanks to the transient shunt aiforded by AND ciruit & the values of the clock pulses 1-, a can change without this causing the value appearing at output a to hange. The holding stage & maintains the value at utput u, even when the clock pulse ,7, after having asumed the value L, thereafter assumes the value 0. With is change, the clock pulse :=L and if, for. example,

lie value at output a was L, this output will remain qual to L because 1; and hence the output of holding tage & =L.

The counter unit according to FIGURE 8 shows two hose output, in turn, is connected to the OR NOT ciruit E. These components serve to form and amplify 1e outgoing carry. Similarly, the AND circuit &' con.-

titutes thefholding stage, the AND circuit & the tranient shunt stage, and AND circuit &' the input stage,

1e outputs of these circuits being connected to the OR ircuit v, whose output, in turn, is connected to the )R NOT circuitE'. These components serve to form nd amplify the sum. The OR circuit v" will be described iter'.

The AND'circuit 8: constituting the holding stagev of he carry circuit, has applied to it the clock pulse 1- as lell as the fed back signal u appearing at the output a f the OR NOT circuit E. The AND circuit & constiuting the transient-shunt stage, has applied to it the signal Y appearing at output a, as well as the input signal which tself is made up of two components. ndicated by the encircled leads, consists of a, and u,,,, rom which a is formed. This corresponds to the arangernent depicted in FIGURE .7. In FIGURE 8, a,

This input signal,

respectively.

is'the output. of :the output storage device AS, at Whichthe circuit which, technically, constitutes the overall storage unit of which the output storage device AS is. a part: The result appearing at a, and the applied incoming carry u thus constituteinput signals which are combined with each other via the AND circuits 8: & thereby forming the.

The AND circuit & constituting the input stage, also has the clock pulse 1- applied to it. The

outgoing carry u 14,, and as. Which are the incoming carry and theoutput signal of the intermediate storage device ZS, respectively. The input stage & also has the clock pulse r applied to it. The holding stage & is connected in the same manner as holding stage.& except'that the applied clock pulse is The transient shunt stage &.' has appliedto itthe output a, of the output storage device AS and the negated outgoing carry'fi iof the'intermediate storage'device ZS. Finally, the counter canbe reset to its startingposition (a,,=0) by applying to the AND circuit &" an erasing signal 1:0, as well as by applying 1- 1 and u ,,.=0.

The outgoing carry u is formed in the intermediate.

storage/device ZS.- The input'stage &; has applied to it the values of L1,, and E so as to form the sumf According to the second line of. Table 2, the sum s =L is formed when u and .H,,,=L. According to line 3 of Table 2, the sum s, Willalso be equalto L when a, and ii- ,,=L.

It will be seen thatithe input and transient-shunt stages &' &" of the counter according to FIGURE 8 have ap plied .to them the values appearing at u 5 and a in an storage device AS. The value s, is'thus formed at the output of OR circuit v.

FIGURE 10'shows the timed relationship .of the clock pulsesn- 1 ,1- aand the erasing pulses l, T. The value 0 can, for example,.be equal to a given negative voltage and the value L be equal to a .givenpositive voltage,- or

vice versa.

The counter can be erased, i.e., reset, when the clock 1 pulses the incoming carry signal it and the erasing signal I are made equal to 0. When the clock pulses 7- 2,;0, theholding action via holding stages & &' is discontinued.

It will be understood that the above description of the present invention is susceptible to various; modifications,

changes, and adaptations, and thesame are intended to.

If the inputs of these stages '&' &" 'have the value L, and if also the additional inputs 1- I become be comprehended within the meaning and range of equivalents of the appended claims.

What is claimed is:

1. In an electric binary counter at whose outputs there appear signals in natural binary code and in parallel representation, the combination which comprises:

(a) a separate adder associated with each binary digit, each adder having a sum circuit and a carry circuit, the carry circuits of all adders being galvanically coupled with each other;

(b) a separate, clock pulsable output storage device associated with each respective adder, each storage device having an input connected to the sum circuit of its respective adder and an output connected to feed the sum signal back into an input of said respective adder;

(c) means for constantly applying the value L as one of the binary signals applied to the adder associated with the lowest binary digit;

((1) a separate, clock pulsable intermediate storage device associated with each binary digit, each intermediate storage device having an input connected to receive said output from the respective output storage device and an output connected to deliver the sum signal to said input of the respective adder;

(c) said carry circuit of each adder being separate from said sum circuit and being connected ahead of the respective intermediate storage device, the latter being an amplifier for amplifying the carry signal;

(f) said sum circuit of each adder being connected ahead of the respective output storage device, the latter being an amplifier for amplifying the sum signal; and

(g) said ca-rry circuit of said adder and said intermediate storage device being combined into a first multiple-component logic circuit and said sum circuit of said adder and said output storage device 'being combined into a second multiple-component logic circuit, said first and second multiple-component logic circuits being similar to each other.

2. The combination defined in claim 1 wherein said carry circuit comprises three AND-circuits constituting a holding stage, a transient shunt stage, and an input stage,

respectively, and said intermediate storage device comprises an OR/ OR NOT-circuit, the outputs of said AND- circuits being connected to said OR/OR NOT-circuit from whose afi'irmed output the outgoing carry signal is taken oif; wherein said sum circuit comprises three further AND-circuits constituting a holding stage, a transient shunt stage, and an input stage, respectively, and said output storage device comprises a further OR/ OR NOT- circuit, the outputs of said last-mentioned three AND- circuits being connected to said last-mentioned OR/OR NOT-circuit from whose affirmed output the result of the sum formation appears; wherein said input and shunt stages of said carry circuit are connected (1) to the output of the respective output storage device to receive the sum signal and (2) to receive the incoming car-ry signal arriving from the preceding digit; wherein saidinput stage of said sum circuit is connected (1) to receive the incoming carry signal arriving from the preceding digit and (2) to receive the negated outgoing carry signal; and wherein said shunt stage of said sum circuit is connected (1) to receive the negated outgoing carry signal and (2) to the output of said respective output storage device to receive said sum signal.

3. The combination defined in claim 1 wherein said adders are half-adders.

References Cited by the Examiner UNITED STATES PATENTS 2,803,401 10/1950 Nelson 235-175 2,962,212 6/ 1956 Schneider 235-92 3,125,675 3/1964 Jeeves 235175 3,125,676 3/1964 Jeeves 235175 3,185,822 6/1965 Davis 235-175 OTHER REFERENCES Arithmetic Operations in Digital Computers, by R. K. Richards, pp. 196-198, published 1955 by D. Van Nostrand Co., Inc, N.Y. 10, N.Y.

DARYL W. COOK, Acting Primary Examiner.

MALCOLM A. MORRISON, Examiner.

I. F. MILLER, Assistant Examiner. 

1. IN AN ELECTRIC BINARY COUNTER AT WHOSE OUTPUTS THERE APPEAR SIGNALS IN NATURAL BINARY CODE AND IN PARALLEL REPRESENTATION, THE COMBINATION WHICH COMPRISES: (A) A SEPARATE ADDER ASSOCIATED WITH EACH BINARY DIGIT, EACH ADDER HAVING A SUM CIRCUIT AND A CARRY CIRCUIT, THE CARRY CIRCUITS OF ALL ADDERS BEING GALVANICALLY COUPLED WITH EACH OTHER; (B) A SEPARATE, CLOCK PULSABLE OUTPUT STORAGE DEVICE ASSOCIATED WITH EACH RESPECTIVE ADDER, EACH STORAGE DEVICE HAVING AN INPUT CONNECTED TO THE SUM CIRCUIT OF ITS RESPECTIVE ADDER AND AN OUTPUT CONNECTED TO FEED THE SUM SIGNAL BACK INTO AN INPUT OF SAID RESPECTIVE ADDER; (C) MEANS FOR CONSTANTLY APPLYING THE VALUE L AS ONE OF THE BINARY SIGNALS APPLIED TO THE ADDER ASSOCIATED WITH THE LOWEST BINARY DIGIT; (D) A SEPARATE, CLOCK PULSABLE INTERMEDIATE STORAGE DEVICE ASSOCIATED WITH EACH BINARY DIGIT, EACH INTERMEDIATE STORAGE DEVICE HAVING AN INPUT CONNECTED TO RECEIVE SAID OUTPUT FROM THE RESPECTIVE OUTPUT STORAGE DEVICE AND AN OUTPUT CONNECTED TO DELIVER THE SUM SIGNAL TO SAID INPUT OF THE RESPECTIVE ADDER; (E) SAID CARRY CIRCUIT OF EACH ADDER BEING SEPARATE FROM SAID SUM CIRCUIT AND BEING CONNECTED AHEAD OF THE RESPECTIVE INTERMEDIATE STORAGE DEVICE, THE LATTER BEING AN AMPLIFIER FOR AMPLIFYING THE CARRY SIGNAL; (F) SAID SUM CIRCUIT OF EACH ADDER BEING CONNECTED AHEAD OF THE RESPECTIVE OUTPUT STORAGE DEVICE, THE LATTER BEING AN AMPLIFIER FOR AMPLIFYING THE SUM SIGNAL; AND (G) SAID CARRY CIRCUIT OF SAID ADDER AND SAID INTERMEDIATE STORAGE DEVICE BEING COMBINED INTO A FIRST MULTIPLE-COMPONENT LOGIC CIRCUIT AND SAID SUM CIRCUIT OF SAID ADDER AND SAID OUTPUT STORAGE DEVICE BEING COMBINED INTO A SECOND MULTIPLE-COMPONENT LOGIC CIRCUIT, SAID FIRST AND SECOND MULTIPLE-COMPONENT LOGIC CIRCUITS BEING SIMILAR TO EACH OTHER. 